EE1-IPRJ EIE1 Project
Lecturer(s): Prof George Constantinides; Dr Christos BouganisAims:
The aim of the project is to expose the students to digital hardware design using a high-level language and to briefly introduce a number of important concepts and techniques from hardware design.
Learning Outcomes:
By the end of the project, students should be able to:
a) understand basic image processing tasks,
b) describe and understand the main design flow in digital hardware design,
c) identify parts of an application that can be parallelized and be able to express this parallelism within a programming environment,
d) understand some of the restrictions imposed by the system architecture,
e) explain how a pipeline works and be able to construct a pipeline in hardware,
f) understand the double buffering technique, to identify potential use of it, and to construct it,
g) describe the basic building blocks of an FPGA and be able to explain how certain high-level functionality can be mapped on them.
Syllabus:
Introduction to basic image processing using hardware; examples of convolution, edge detection and colour conversion; Using Software to Design Hardware; Introduction to Catapult C language; Algorithmic development and Implementation flow; Group project: Parallel Image Processing
Assessment:
Coursework contribution: 100%
Term: N/A
Closed or Open Book (end of year exam): Open
Coursework Requirement
Laboratory Experiment
Oral Exam Required (as final assessment): yes
Prerequisite: None required
Course Homepage: unavailable
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