EE3-05 Digital System DesignLecturer(s): Dr Christos Bouganis
To enable students to design digital systems of medium complexity, and to teach how to implement the design with FPGA/CPLD devices, memory devices and microprocessors. To enable students to design systems that obey timing constraints and are testable.
By the end of the course, students would be able to:
* Go about designing complex, high speed digital systems (not just circuits)?
* Use some of the modern CAD tools to help with the design
* Implement such designs using programmable logic (e.g. FPGAs)
* Read data sheets and make sense of them
* Effective design with digital building blocks (such as memory chips, microprocessors, arithmetic circuits etc.)
* Interface to microprocessors and computers (from hardware point of view)?
* Deal with testing of complex systems?
In this course the principles and techniques for designing reasonably large digital circuits and systems will be studied. Based on the design of a practical medium-sized circuit, and a number of smaller examples, the course covers the following topics:
1) System bus interfacing;
2) FPGA architectures;
3) Multiplier circuits;
4) Dynamic memory interfacing and DMA control circuits;
5) Timing issues in digital circuits: hazards, metastability and races;
6) High speed digital design techniques;
7) JTAG standard and design for testability.
This course is a good follow-on course to E3.06 VHDL and Logic Synthesis
80% coursework, 20% class test in Spring Term
Coursework contribution: 80%
Closed or Open Book (end of year exam): Closed
To be announced
Oral Exam Required (as final assessment): N/A
Prerequisite: None required
Course Homepage: unavailable