EE3-06 VHDL and Logic Synthesis
Lecturer(s): Dr Tom ClarkeAims:
This course teaches students how to use VHDL compilers, simulation and synthesis tools to describe and verify digital systems in a technology-independent fashion.
Learning Outcomes:
Use RTL design technique. Write RTL descriptions in a synthesisable subset of VHDL. Design, and write in VHDL, testbenches for digital hardware. Analyse simple VHDL code to determine synthesis and simulation efficiency.
Syllabus:
Part 1: VHDL
Modelling of hardware: model of behaviour, time and structure.
Major VHDL constructs: entity declarations, architecture bodies, subprograms, packages and 'use' clauses.
Basic VHDL data types: literals, scalars, vectors.
Behavioural description: processes, activation and suspension of processes, sequiential assignments, signal assignments, variable assignments, sequential control, procedure and function calls, concurrent statements.
Structural description: parts, component instantiation, configuration specifications, busses.
Access types: files, file I/O
Part 2
Testing and verification: VHDL testbenches. Procedural abstraction. Exhaustive, random, ad-hoc testing methods. Test coverage metrics.
Part 3: Synthesis
Multi-level logic minimisation techniques: boolean optimisation. Critical path optimisation.
High level synthesis: state minimisation in FSM.
Technology mapping: gate arrays, FPGA, PLDs.
Assessment:
80% coursework, 20% class test in Spring Term
Coursework contribution: 80%
Term: Spring
Closed or Open Book (end of year exam): Closed
Coursework Requirement
To be announced
Oral Exam Required (as final assessment): N/A
Prerequisite: EE3-05 - Digital System Design
Course Homepage: https://intranet.ee.ic.ac.uk/t.clarke/vhdl/
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