Department of Electrical & Electronic Eng.  (EEE)   BEng & MEng 2nd Year

ELEC50001 Circuits and Systems (Oct - Dec 2025)
Professor Peter Y. K. Cheung


Aims & Objectives

This module builds on the first-year modules relating to analogue and digital circuits, computer architecture, and programming, to teach students how to analyse and design electronic circuits with a system level perspective. The aim of this module is to provide students with the theoretical foundations, the design techniques and hands-on experiences of acquiring physical analogue signals, pre-processing them, converting into digital form, then process these in a digital programmable hardware on a Field Programmable Gate Array (FPGA). Unlike last year's module on circuits, year students will learn to process signals that have noise and electronic hardware that are non-ideal.

By the end of the course, you should be able to:

This course is supported by 6 Laboratory Experiments based a Lab-in-a-Box to enable students to conduct all the experiments in-person and at home.

RECOMMENDED TEXTBOOKS

Practical Electronics for Inventors (~£30)

COURSE SCHEDULE AND CONTENTS

Date

Topics
Resources

7  Oct


Lecture 1 - Introduction to Circuits & Systems

        1st half

Lecture 2 - Amplification & Single-Rail Op-amp

         2nd half


Problem Sheet 1    (solutions)

MCP601 datasheet  

Course Planning Document

Year 1 Introduction to LTSPICE

Keysight Scope Documents
(user's manual)


Tenma multimeter manual  

13 Oct


Lab 1 - Amplification


LTSPICE  hotkeys  

Guidelines on Logbook  

MCP6001/2 data & model    

AP431i data & model    

PAM8302 datasheet  

PAM8302 module  


14  Oct


Lecture 3 - Understanding Op-amp Specifications

        1st half

Lecture 4 - Understanding Op-amp Models

         2nd half

LTspice essential tutorials  

LTspice wiki  

20  Oct


Lab 2- Op-amp Applications 


Microphone datasheet    

IN5817 schottky diode data    


21  Oct


Lecture 5 - Op-amp Applications

         1st half

Lecture 6 - Active Filters

         2nd half

Problem Sheet 2    (solutions)

TI's Op-amp Cookbook    

Understand Op-amp Specifications    

Analog Devices Electronics wiki    

Analog Devices Op-Amp Applications    

Analog Pocket Reference Guide  

27  Oct


For those who finished Lab 2 early:

Lab 3 - Introducing DE10-Lite
 


Lab 3 Task 1 solution (zipped)    

Pin Assignment File    

Updated USB Blaster Driver    

Intel Quartus Prime Lite Download  


28  Oct


Lecture 7 - Digital Designing with FPGA

        1st half


Lecture 8 - SystemVerilog HDL

         2nd half

Altera FPGA Support Resources    

MAX10 Device Architectures    

DE10-Lite Resource Centre  

3-4 Nov


Mid-term Lab Oral - Guidelines and Schedule    


Lab Oral Schedule    

Lab Oral Marksheet    


10 Nov


Lab 4 - Sequential Circuits    


Lab4 Task1 solution (zipped)    

Lab4 Task2 solution (zipped)    

Lab4 Task3 solution (zipped)    

bin2bcd_16.sv    

clktick.sv    

Updated USB Blaster Driver    

11  Nov


Lecture 9 - Counters and Shift Registers

        


Problem Sheet 3    (solutions)

SystemVerilog Cheatsheet    

17 Nov


Lab 5 - DAC and Function Generator    


pwm.sv & spi2dac.sv    

MCP4921 datasheet    

Lab5 solutions    

18  Nov


Lecture 10 - Digital to Analogue Conversion

           1st half

Lecture 11 - Finite State Machines

           2nd half

Problem Sheet 4    (solutions)

Data Converter Handbook    

24 Nov


Lab 6 - ADC and echo synthesizer    

Lab 6 codes to download    

MCP3201 ADC datasheet    

Lab 6 solutions    

Audio files:  clapping.mp3,   hello.mp3,   hg2g.mp3hg2g(short).mp3


25  Nov


Lecture 12 - A-to-D Conversion

         2nd half

Lecture 13 - Lab 6 & Challenges explained

         2nd half

The Challenges    

Problem Sheet 5    (solutions)

Sinewave Generator in Matlab  

Rom data file   

2  Dec


Lecture 14 - Timing Constraints

         1st half

Lecture 15 - memories

         2nd half

Problem Sheet 6    (solutions)

Problem Sheet 7    (solutions)

Bonus Lecture
SPI to DAC module explained

     

9 -10 Dec


End-of-Term Lab Oral - Guidelines and Schedule    



Module Evaluation Survey    


LECTURE NOTES 

  • Lecture 1 - Introduction to circuits & systems (notes)
  • Lecture 2 - Amplification and Single-Rail Op-amp (notes)
  • Lecture 3 - Understanding Op-amp Specification (notes)
  • Lecture 4 - Understanding Op-amp Models (notes)
  • Lecture 5 - Op-amp Applications (notes)
  • Lecture 6 - Active Filters (notes)
  • Lecture 7 - Digital Design with FPGAs (notes)
  • Lecture 8 - SystemVerilog HDL (notes)
  • Lecture 9 - Counters and Shift Registers (notes)
  • Lecture 10 - DAC Conversion (notes)
  • Lecture 11 - Finite State Machines (notes)
  • Lecture 12 - Analogue-to-Digital Conversion (notes)
  • Lecture 13 - Lab 6 & Challenges Explained (notes)
  • Lecture 14 - Timing Constraints (notes)
  • Lecture 15 - memories (notes)
  • Lecture 16 - spi2dac explained (notes)
  • LAB INSTRUCTIONS

  • Lab 1- Amplification & Single-rail Op-Amp
  • Lab 2 - Op-amp Applications
  • Lab 3 - Introduction to Quartus & DE10-Lite
  • Lab 4 - Sequential Circuits
  • Lab 5 - DAC and Function Generator
  • Lab 6 - ADC & Echo Synthesizer
  • Challenges
  • PROBLEM SHEETS

  • Problem Sheet 1 (solutions)
  • Problem Sheet 2 (solutions)
  • Problem Sheet 3 (solutions)
  • Problem Sheet 4 (solutions)
  • Problem Sheet 5 (solutions)
  • Problem Sheet 6 (solutions)
  • Problem Sheet 7 (solutions)

  • This page is maintained by Peter Cheung
    Last updated   2 Dec 2025