EIE2 Instruction Architectures

ELEC50010 Instruction Architectures & Compiler (IAC) - Autumn Term 2025

Week starting	Sessions	Resources
6 Oct	Lecture 1 - Introduction to IAC Lab 0 - Setting up the environment Lab Partnership Survey	Future of RISC-V has no Limits RISC-V: open-hardware revolution Git & Github in 30 minutes Markdown Crash Course Markdown Cheatsheet Git Cheatsheet Hack your brain with Obsidian Obsidian download page
13 Oct	Lecture 2 - Hardware Design with System Verilog Lecture 3 - Verilator, Testbench and Vbuddy 2nd half Lab 1 - SystemVerilog & Verilator	Verilator Resources Synthesizable SystemVerilog Cheatsheet
20 Oct	Lecture 4 - Counters, Shift Registers & Memories 1st half Lecture 5 - Finite State Machines 2nd half Lab 2 - Signal Generator
27 Oct	Lecture 5 - Finite State Machines 1st half Lecture 6 - RISC-V ISA 2nd half Lab 3 - Finite State Machines
3 Nov	Mid-term Quiz
12 Nov	Lecture 7 - RISC-V Microarchitecture Lab 4 - A Reduced RISC-V CPU	Project Team Allocation
17 Nov	Lecture 8 - Pipelined Processor 1st half Lecture 9 - Memory Hierachy & Cache 2nd half
25 Nov	Lecture 10 - Virtual Memory 1st half Lecture 11 - Additional Topics 2nd half Project Brief	Sample Team statement Sample Individual statement
12 Dec	Team Project Deadline at 23.59.	Module Evaluation Survey