EIE2 Instruction Architectures

ELEC50010 Instruction Architectures & Compiler (IAC) - Autumn Term 2024

Week starting	Sessions	Resources
7 Oct	Lecture 1 - Introduction to IAC Lab 0 - Setting up the environment Lab Partnership Survey	Future of RISC-V has no Limits RISC-V: open-hardware revolution Git & Github in 30 minutes Markdown Crash Course Markdown Cheatsheet Git Cheatsheet Hack your brain with Obsidian Obsidian download page
14 Oct	Lecture 2 - Hardware Design with System Verilog Lecture 3 - Verilator, Testbench and Vbuddy 2nd half Lab 1 - SystemVerilog & Verilator	Verilator Resources Synthesizable SystemVerilog Cheatsheet
21 Oct	Lecture 4 - Counters, Shift Registers & Memories Lab 2 - Signal Generator
29 Oct	Lecture 5 - Finite State Machines Lecture 6 - RISC-V ISA Lab 3 - Finite State Machines
6 Nov	Mid-term Quiz Sample Quiz Questions Sample Quiz Questions with answers
12 Nov	Lecture 7 - RISC-V Microarchitecture Lab 4 - A Reduced RISC-V CPU	Project Team Allocation
19 Nov	Lecture 8 - Pipelined Processor 1st half Lecture 9 - Memory Hierachy & Cache 2nd half
26 Nov	Lecture 10 - Virtual Memory Project Brief	Excellent Team statement from 2 years ago Excellent Individual statement from 2 years ago
3 Dec	Lecture 11 - Additional Topics