 Department of Electrical &
Electronic Engineering Electrical & Electronic Eng.
(EEE) BEng & MEng 2nd Year Frequently Asked Questions (FAQ) page |
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A. Installation of Quartus and DE0 Board
1. The version of Quartus that came with the DE0 Board is v9.0, and the current version from Altera is v11sp1. What are the differences and which one should I use?
Obiviously v11sp1 is more up todate than v9.0. However, I recommend you to use v9.0 because:
2. I use a Mac, not a PC. Will Quartus and DE0 work with a Mac?
Yes, there are TWO solutions: 1) Make your Mac dual boot using bootcamp, and create a partition for Windows XP or Windows 7, 2) Use a Virtual Machine (VM) Programme with your Mac OSX. The second solution is my personal preference because of its seamless integration with OSX, but VM program (either Parallels or VMware) costs you money. There is also a Open Source Virtual Machine called Virtual Box. All the practical exercises have been tested in Virtual Box and they all worked perfectly. (Contribution from Dario Magliocchetti-Lombi.)
I personally use a MacBook Pro running Parallels virtual machine.
Everything run perfectly with it: Quartus II v9.0 and v11sp1, USB Blaster driver (used to configure or program the DE0 board) and DE0 Control Panel software.
3. When I switch on the DE0 board, it asks me for a driver, which it cannot find on the DVD or from anywhere else. Where is the driver?
The DE0 uses the USB port to communicate with your computer. The driver you need is known as "USB-Blaster". This can be found under the directory where Quartus is installed on your computer. For example, if Quartus is installed on c:\alter\90\quartus, in this folder, you will find a directory \drivers. Specify this as the directory that Windows should search for a driver. You then select USB-Blaster as the driver to install and you are off! Remember: you only need to do this once.
4. I use Windows 7 and have difficulties installing the DE0 driver. What should I do?
1. Plug in your DE0 board to the USB port, and turn it ON (red button on DE0).
2. Windows 7 will ask you for drivers. Do not search, but provide it from your disk. Here is a driver you can use.
3. Windows 7 will complain about the digital signature has expired - ignore this can select "continue anyway".
4. After you install the driver, you should be able to setup the board under quartus.
4. When I try to run the DE0 Control Panel on Windows 7, I get two error messages: a) quartus_prm download fail(0 sec); b) download SOPC file (DE0_ControlPanel.sof) fail!
USB Blaster was not being recognized by Quartus because of the digital signature problem.
To get rid of this problem, restart windows 7, pressed F8 to get into "boot" menu, then selected "disable driver signature enforcement". This allows unsigned drivers to be installed. After that, the DE0 control panel should work. (Contribution from Taoda Hong.)
B. Questions relating to Exercise 1 & 2
1. The waveform editor software has been removed from version 11. How can I simulate the design?
You have two choices: install version 9 (that came with the DE0 board), which contains the waveform editor, or create a Verilog testbench. Very shortly, I will be showing the class how to use Verilog HDL. You will find that this is by far the better way of simulating and debugging your design. Since the integration of DE0 to Quartus software is extremely good, I found that the easiest way to test your design is actually load your design onto the DE0 and test it on the board itself. This at least works very well for the eariler practical exercise.
2. How can I produce a symbol for my module?
Open the schematic or Verilog file for your module. Then use the follow command: File > Create/Update > Create Symbol file for the current file. After that you will be able to pick up the symbol at a high level schematic entry and connect this up as required. Of course, symbol file creation is NOT necessary if you only use Verilog HDL to specify your design.
3. Using the pin assignment editor is very tedious. Is there are fast way to assign pin locations and i/o standards?
Yes, on your first compilation of your design, Quartus produces a ".qsf" file, which contains various assigments. You can open this file within Quartus editor, and open another file that contains all the pin assignments used in DE0. You can then cut-and-paste the relevant pin across to your design's .qsf file and the save it. When you then next compile your design, the system will know the correct pin assignment. Note that you need to assign two things for each pin you used: the pin location, and its I/O standard. For example:
set_location_assignment PIN_J6 -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
4. When I compile my module in Verilog, it says that "Top level file missing". What is a top-level file?
Your Verilog module is just like a component, it has to be incorporated into a complete circuit. When you create a new project, you are asked to specify the top level file name (which you could call anytime, such as "top"). This is the file that instantiate all your components to form the circuit. A top-level file could be a schematic file, or a HDL file. My preference is to use Verilog to specify everything, including the top-level file.
5. What is the difference between "compile" and "analyse and elaborate" my design, and which should I use?
Compiling performs everything, including synthesis, optimisation, placement of components and routing the interconnections etc., and will take much longer. It will also generate many irrelevant warning messages. Therefore debugging your Verilog design using "compile" command is not that effective. "Analyse and Elaborate" is much faster (may be 5 times quicker), and performs essential checks on your Verilog description. If you sort out all error and warning messages (so that you have none), your design is much more likely to work.
C. Questions relating to Exercise 3 - Digital Clock
1. I use the buttons to set my clock to current time by incrementing minute and hour setting by 1 for each press. But it keep increment by a random amount. Why?
All switches have "switch bounces", that is the contact open and clock many times before settling to the final state. There all switches will generate a oscillatory signals for a while. Normally, one uses a Set-Reset flipflop to debounce a switch (see E1 Digital Electronics notes, lecure 9, slide 13). However, SR flipflop is NOT available on Cyclone III FPGAs. Here is a button-debouncer module (in Verilog) which uses a long shift-register to debounce a button or a switch.
