University of London

Department of Electrical & Electronic Engineering
M.Eng. Fourth Year Course

Digital IC Design

CHIPS designed by previous students

Asynchronous FIFO - This chip implements a full asychronous First-in-First-out buffer with Muller style pipeline control. It is completely free of any clock signals. See J. Sparso, "Asynchronous circuit design - a tutorial", in Principles of asychronous circuit design - A system perspective, Chapter 2, Kluwer Academic Publishers, 2001.
biquad - This chip implements a second order IIR filter (bi-quadratic) using distributed arithmetics. See S.A. White, "Applications of Distributed Arithmetic to Digital Signal Processing", IEEE ASSP Magazine, vol. 6(3), pp. 4-19, July 1989.
Booth Multiplier - This chip implements the modified booth multipler algorithm for a 4x4 bit (8-bit product) parallel multiplier. See Wen-Chang Yeh; Chein-Wei Jen, "High-speed Booth encoded parallel multiplier design", IEEE Transactions on Computers, Volume: 49 , Issue: 7 , July 2000, Pages:692 - 701.

Cordic processor - This chip implements a standard processor using the cordic algorithm to compute trigonometric functions. See Volder, J.E. The CORDIC trigonometric computing technique. IRE Trans. Electron. Comput., EC-8, 3 (Sept. 1959), 330-334 and Walther 71 Walther, J.S. A unified algorithm for elementary functions. In Proceedings of AFIPS 1971 Spring Joint Computer Conference, vol. 38, AFIPS Press, Arlington, Va., 1971, pp. 379-385.

Image correlator - This chip implements a grey-scale image correlator for real-time video applications.
Finite Impulse Response Filter - This chip implements a FIR filter implemented with fixed coefficients.
Time integrating correlator - This chip implements a time integrating correlator that is suitable for spread-spectrum applications. See D. Beeler, H. Kaufmann, "Time integrating correlator (TIC) for real-time processing of spread-spectrum signals", IEEE Custom Integrated Circuit Conference (CICC) 1990.
Window Frame Store (WFS) - This chip implements a novel two dimensional storage element designed for motion vector estimation in real-time video compressors. It stores a 8X8 window that is moving over a large search space, and provide maximum parallelism for block based computation.
Median Filter - This chip implements a 5-tap median filter using systolic architecture. It is the first student design that uses Electric instead of Magic or GDT software for the design. Specification of the design can be found here.


This page is maintained by Peter Cheung
Last updated: 16 Jan 2005.