Department of Electrical & Electronic Engineering

Electrical & Electronic Eng.         (EEE)        BEng & MEng 2nd Year
Electronic and Information Eng.  (EIE)
          BEng & MEng 2nd Year

E2 Lab - Experiment VERI
(13 Nov to 15 Dec 2017)

Professor Peter Y. K. Cheung

Aims & Objectives

This experiment is designed to support my second year course E2.1 Digital Electronics II (COURSE WEBPAGE HERE).
The experiment runs from Monday 14th of November to Friday 9th of December 2016.
Lab student pairing can be found here.
The Lab Supervision Team can be found here.

The VERI Experiment Handbook (all four parts) can be found HERE.

Useful Resources

Part 1 - Schematic vs Verilog

Ex1 solution ( - need to unzip
Incomplete version of 7-segment decoder (
Verilog code for bin2bcd modules (zipped)
Ex4 solution (
Verilog Quick Reference Card (PDF)

Part 2 - Counters & FSMs

Instruction to set up Modelsim
Ex8 solution (

Verilog code for bin2bcd modules - (zipped)

Part 3 - DAC & Tone Generator

spi2dac and spi2adc (zipped)
Test Bench for spi2dac.v (DO file)
Analogue I/O Card schematic diagram
    DAC - MCP4911
    ADC - MCP3002
    Opamp - MCP604
Sinewave Generation (python, matlab)
ROM initialization file (rom_data.mif)
Ex11 solution (
Ex14 solution (
Ex15 solution (

Part 4 - ADC/DAC & Echo Synthesizer

ex16_proto (zipped file)
Simple audio files (clapping.mp3, hello.mp3)
Better audio files hg2g_short.mp3, hg2g_full.mp3)
ex19 variable delay echo - solution (

ex20 Voice corruptor - solution (

DE1-SoC Reference Manuals

DE1-SoC Board from Terasic
DE1-SoC Learning Roadmap
DE1-SoC Getting Started Guide
DE1-SoC My First FPGA
DE1-SoC User's Manual
DE1-SoC Schematic Diagram

Cyclone V Device Handbooks

Cyclone V Device Overview
Cyclone V Device Handbook Vol 1: Device Interfaces and Integration

Cyclone V Device Handbook Vol 2: Transceivers
Cyclone V Device Handbook Vol 3: Hard Processor System Technical Reference Manual

Quartus Related Links
Quartus Prime Lite Web Edition (free)
Quartus Tutorial Page (containing MANY tutorials, probably too many. Be selective!)

Verilog Resources

Verilog tutorial by ASIC World

This page is maintained by Peter Cheung
Last updated: 30 Nov 2017