Department of Electrical & Electronic Engineering

Electrical & Electronic Eng.         (EEE)        BEng & MEng 2nd Year
Electronic and Information Eng.  (EIE)
          BEng & MEng 2nd Year

E2.1 Digital Electronics 2
(Oct - Dec 2017)

Professor Peter Y. K. Cheung


Aims & Objectives

The aims of the course are: By the end of the course, you should be able to:

This course is supported a 4-week Laboratory Experiment - Experiment VERI starting in the middle of the Autumn term. You will be working in pairs, using the Terasic/Altera's DE1-SoC board with a daughter board extension. Each pair of students can also sign out one board (every two students) from the EEE Stores. Please return the board by the end of the Spring term in 2018.

Lecture Notes

    Lecture 1  Introduction to digital logic (10 Oct - Panopto recording) (notes 2-per page)
    Lecture 2  Introduction to FPGAs (10 Oct - Panopto recording)
(notes 2-per page)
    Lecture 3  Verilog HDL - Part 1 (17 Oct - Panopto recording pt1 pt2) (notes 2-per page)
    Lecture 4  Verilog HDL - Part 2 (19 Oct - Panopto recording) (notes 2-per page)
    Lecture 5  Counters and shift registers (24 Oct - Panopto recording   pt2) (notes 2-per page)
    Lecture 6  Finite State Machines - Part 1 (26 Oct - Panopto recording) (notes 2-per page)
    Lecture 7  Finite State Machines - Part 2 (31 Oct - Panopto recording)
(notes 2-per page)
    Lecture 8  Timing constraints (2 Nov - Panopto recording , 7 Nov - recording) (notes 2-per page)
    Lecture 9  D-to-A converters (ADI Handbook Chap 3) (9 Nov - Panopto recording) (notes 2-per page)
    Lecture 10  Experiment VERI - an overview (9 Nov - Panopto recording) (notes 2-per page)
    Lecture 11  A-to-C converters (ADC architectures - A tutorial) (16 Nov - Panopto recording) (notes 2-per page)
    Lecture 12  Serial Peripheral Interface (SPI) (21 Nov - Panopto recording) (R12.1 DAC datasheet) (notes 2-per page)
    Lecture 13  Memory Interface (23 Nov - Panopto recording28 Nov - Part 2)
(notes 2-per page)
    Lecture 14  FPGA Embedded Memory (28 Nov - Panopto recording) (notes 2-per page)
    Lecture 15  Adders and DSP Block (30 Nov - Panopto recording) (notes 2-per page)
    Lecture 16  The Final Chapter (5 Dec - Panopto recording) (notes 2-per page)

Tutorial Problem Sheets

Tutorial Problems
Useful Resources

Sheet 1 (solution 1)

R1.1 FPGA and CPLD Architectures: A Tutorial
R1.2 Cyclone V Device Handbook (vol 1)
R1.3 Introduction to Quartus II Software
R1.4 DE1 User's Manual

Sheet 2 (solution 2)
 
Sheet 3 (solution 3)
 
Sheet 4 (solution 4)
 
Sheet 5 (solution 5)
 
Sheet 6 (solution 6)
 

Problem Classes

Problem Class 1 (24 Oct 2017) (Panopto recording)
Problem Class 2 (31 Oct 2017) (Panopto recording)
Problem Class 3 (7 Nov 2017) (Panopto recording)

Problem Class 4 (21 Nov 2017) (Panopto recording)
Problem Class 5 (21 Nov 2017) (Panopto recording)

Past Examination Papers

June 2016
June 2017

The Laboratory Experiment (Experiment Webpage HERE)

This course is supported by a 4-week experiment in the Laboratory.
Details of this experiment can be found HERE.

Other DE1 & Cyclone V Resources

Quartus Prime Software free web-edition (Download page)
Quartus & DE1-SoC Tutorial Page (containing MANY tutorials, probably too many. Be selective!)

Cyclone V Device Handbooks

Vol 1: Device Interface & Integration
Vol 2: Transceivers
Vol 3: Hard Processor System


Useful links

Verilog HDL Quick Reference Card
A very good tutorial on IEEE Logic Symbols
An excellent tutorial on Verilog HDL

Altera's free tutorial on Verilog HDL (interactive video class lasting 45 minutes)
On-line Verilog HDL Quick Reference Guide (free)


This page is maintained by Peter Cheung
Last updated: 5 Dec 2017