E2.1 Digital Electronics 2

Department of Electrical & Electronic Engineering

Electrical & Electronic Eng. (EEE) BEng & MEng 2nd Year
Information Systems Eng. (ISE) BEng & MEng 2nd Year

E2.1 Digital Electronics 2 (Autumn 2011)

Professor Peter Y. K. Cheung

Aims & Objectives

The aims of the course are:

To enable you to analyse and synthesize small synchronous digital systems.
To give an understanding of factors that limit the performance of digital systems.
To give an understanding of how digital systems communicate with each other and with their external environment.

By the end of the course, you should be able to:

analyse the operation of synchronous digital systems
synthesize a synchronous digital system to meet a specification
determine the worst-case propagation delay of a combinational circuit
evaluate the performance of A/D and D/A conversion circuits
design arithmetic circuits to meet a specification and determine the propagation delay
design some digital circuits on real hardware

This course is supported by Terasic/Altera's DE0 board with a daughter board extension. Each student can sign out one board for the term from EEE Stores.
Please return the board by the end of the Spring term.

Textbook “Digital Systems – Principles and Applications”, 9th Ed, R. J. Tocci and N. S. Widmer, Prentice Hall, ISBN: 0131219316, 2004 (£45)

Lecture Notes

Introduction & Preliminaries
    Lecture 1 Basics & background
    Lecture 2 FPGAs, Design Flow & DE0 Board
    Lecture 3A Verilog HDL - Part 1
    Lecture 3B Verilog HDL - Part 2
Interfacing Digital Systems
    Lecture 4 Synchronous bit-serial interfacing
    Lecture 5 Memory interfacing
    Lecture 6 FPGA Embedded Memory (R6.1, R6.2, R6.3, R6.4)
Interfacing with Analogue Systems
    Lecture 7 Digital-to-Analgue Conversion
    Lecture 8 Analogue-to-Digital Conversion
    Lecture 9 Practical Data Converters (R9.1, R9.2)
Synchronous State Machines & Control Circuits
    Lecture 10 Control Logic
    Lecture 11 Synchronous state machine analysis
    Lecture 12 Synchronous state machine design
    Lecture 13 State Machine in Verilog
Arithmetic Circuits
    Lecture 14 Adder Circuits
    Lecture 15 Fast Adder Circuits

REVISION LECTURE 1
REVISION LECTURE 2

Tutorial Problem Sheets & Practical Exercises (FAQ page relating to DE0)

Tutorial Problems	Practical Exercises	Resources
Problem 1 (Solution 1)	Practical 1 (Step-by-Step Solution)	Quartus Schematic Tutorial 7_Segment_Decoder file (zipped) DE0 pin assignments
	Practical 2	Verilog Quick Reference Card
Problem 2 (Solution 2)	Practical 3	pin_assignment.txt
Problem 3 (Solution 3)
Problem 4 (Solution 4)	Practical 4	rom_gen.m debounce_oneshot.v
Problem 5 (Solution 5)
Problem 6 (Solution 6)
Problem 7 (Solution 7)

DE0 & Cyclone III Resources

Quartus II Software v11sp1 web-edition (Download page)
Quartus Tutorial Page (containing MANY tutorials, probably too many. Be selective!)
Getting Started with DE0 (PDF)
DE0 User's Manual (PDF)
Cyclone III Handbook (PDF)
FPGA & CPLD Architecture: A Tutorial by Brown and Rose (PDF)
Introduction to Quartus II (PDF)

Problem Classes Handouts

1, 2, 3, 4

Verilog Resources

Verilog tutorial by ASIC World

Useful links

Companion website to Tocci's Textbook.
A very good tutorial on IEEE Logic Symbols
An excellent tutorial on Verilog HDL
Altera's free tutorial on Verilog HDL (interactive video class lasting 45 minutes)

This page is maintained by Peter Cheung
Last updated: 17 May 2012