Department of Electrical & Electronic Eng.  (EEE)   BEng & MEng 2nd Year

ELEC50001 Circuits and Systems (Oct - Dec 2023)
Professor Peter Y. K. Cheung


Aims & Objectives

This module builds on the first-year modules relating to analogue and digital circuits, computer architecture, and programming, to teach students how to analyse and design electronic circuits with a system level perspective. The aim of this module is to provide students with the theoretical foundations, the design techniques and hands-on experiences of acquiring physical analogue signals, pre-processing them, converting into digital form, then process these in a digital programmable hardware on a Field Programmable Gate Array (FPGA). Unlike last year's module on circuits, year students will learn to process signals that have noise and electronic hardware that are non-ideal.

By the end of the course, you should be able to:

This course is supported by 6 Laboratory Experiments based a Lab-in-a-Box to enable students to conduct all the experiments remotely or in-person.

RECOMMENDED TEXTBOOKS

Practical Electronics for Inventors (~£30)

COURSE SCHEDULE AND CONTENTS

Date

Topics
Resources

10  Oct


Lecture 1 - Introduction to Circuits & Systems
(slides, notes)

Problem Sheet 1, MCP601 datasheet, (solutions)

   Lecture recording for this week

Course Planning Document

Keysight Scope Documents
(user's manual)


Tenma multimeter manual  

17 Oct


Lab 1 - Amplification

Lecture 2 - Amplification & Single-Rail Op-amp
(slides, notes)

   Lecture recording for this week

Use of electronic logbook
MCP6001/2/4 datasheet

AP431i voltage reference
LM386 datasheet
8 ohm speaker datasheet

24 Oct


Lecture 3 - Anatomy of an op-amp
(slides, notes)

Lab 2 - Op-amp Applications

Problem Sheet 2 (solutions)  

   Lecture recording for this week

Supplementary notes on LM386
Microphone datasheet

31 Oct


Lecture 4 - Op-amp Applications
(slides, notes)

   Lecture recording for this week

´┐ŻAnalog Devices Electronics wiki
Analog Devices Op-Amp Applications
Tutorial on op-amp (Hard!)

7 Nov


Lecture 5 - Digital Design with FPGAs
(slides, notes)

   Lecture recording for this week


Intel FPGA Resource Centre
MAX10 Device Architecture
DE10-Lite Resource Centre
Intel Quartus Prime Lite (PC)


14 Nov


Lecture 6 - SystemVerilog HDL
(slides, notes)

Problem Sheet 3 (solutions)

Lab 3 - Introduction to Quartus & DE10-Lite

Lab 4 - Sequential Circuits


   Lecture recording for this week

Lab 3 Task 1 solution (zipped)

Pin Assignment File

USB Blaster Driver

Lab4 Task1 solution (zipped)
Lab4 Task2 solution (zipped)
Lab4 Task3 solution (zipped)
bin2bcd_16.sv (zipped)
clktick.sv (zipped)

21 Nov


Lecture 7 - Counter & Shift Register
(slides, notes)

Lecture 8 - DAC Conversion
(slides, notes)

Problem Sheet 4 (solutions)

Lab 5 - DAC & Function Generator

   Lecture recording for this week

pwm.sv & spi2dac.sv (zipped)
MCP4921 datasheet 
Lab5 Task1 solution (
zipped)
Lab5 Task2 solution (zipped)
Lab5 Task3 solution (zipped)
Lab5 Task3x solution (zipped)  
Analog Devices - Data Conversion Handbook

28  Nov

Lecture 9 - Finite State Machines
(slides, notes)

Lecture 10 - A-to-D Conversion
(slides, notes)

Problem Sheet 5 (solutions)
Problem Sheet 6 (solutions)

Lab 6 - ADC & Echo Synthesizer

   Lecture recording for this week

Lab 6 code to download  (zipped)
MCP3201  datasheet
Lab6 Task1 solution (zipped)
Lab6 Task2 solution (zipped)
Lab6 Task2x solution (zipped)
Lab6 Task3 solution (zipped)
Lab6 Task4a solution (zipped)
Lab6 Task4b solution (zipped)
Audio files: clapping.mp3, hello.mp3,  hg2g.mp3
task3 files to download  (zipped)

5 Dec

Lecture 13 - Memories
(slides, notes, recording)


Challenges

spi2dac Explained

Scripts to generate ROM contents
(Matlab, Python)

ROM content file rom_data.mif (zipped

13-14 Dec


Final Lab Oral - Guidelines and Schedule

LECTURE NOTES 

  • Lecture 1 - Introduction to circuits & systems (notes)
  • Lecture 2 - Amplification and Single-Rail Op-amp (notes)
  • Lecture 3 - Anatomy of an op-amp (notes)
  • Lecture 4 - Op-amp Applications (notes)
  • Lecture 5 - Digital Design with FPGAs (notes)
  • Lecture 6 - SystemVerilog HDL (notes)
  • Lecture 7 - Counters & Shift Register (notes)
  • Lecture 8 - DAC Conversion (notes)
  • Lecture 9 - Finite State Machines (notes)
  • Lecture 10 - A-to-D Conversion (notes)
  • Lecture 11 - Echo Synthesizer - Lab 6 Explained (notes)
  • Lecture 12 - Timing Constraints (notes)
  • Lecture 13 - Memories (notes)
  • LAB INSTRUCTIONS (Group Pairing)

  • Lab 1- Amplification & Single-rail Op-Amp
  • Lab 2 - Op-amp Applications
  • Lab 3 - Introduction to Quartus & DE10-Lite
  • Lab 4 - Sequential Circuits
  • Lab 5 - DAC and Function Generator
  • Lab 6 - ADC & Echo Synthesizer
  • Challenges
  • PROBLEM SHEETS

  • Problem Sheet 1 (solutions)
  • Problem Sheet 2 (solutions)
  • Problem Sheet 3 (solutions)
  • Problem Sheet 4 (solutions)
  • Problem Sheet 5 (solutions)
  • Problem Sheet 6 (solutions)
  • Module Evaluation 2022-23 (PDF)


    This page is maintained by Peter Cheung
    Last updated   12 Dec 2023