1 Introduction

1.1 SCMOS Design Rules

In the SCMOS rules, circuit geometries are specified in the Mead and Conway's lambda based methodology [1]. The unit of measurement, lambda, can easily be scaled to different fabrication processes as semiconductor technology advances.

Each design has a technology-code associated with the layout file. Each technology-code may have one or more associated options added for the purpose of specifying either (a) special features for the target process or (b) the presence of novel devices in the design.

2 Standard SCMOS

The standard CMOS technology accessed by MOSIS is a single polysilicon, double metal, bulk CMOS process with enhancement-mode n-MOSFET and p-MOSFET devices [3].

2.1 Well Type

Three technology-codes are used to indicate the well type (substrate) used for fabrication (as shown in Table 1).
 

For our course, we are using Scalable CMOS n-well 0.35 um process similar to that of TSMC 0.35 process.

2.2 SCMOS Options

SCMOS options are used to designate projects that use additional layers beyond the standard single-poly, double metal CMOS. Each option is called out with a designator that is appended to the basic technology-code. The current list is shown in Table 2.
 

The process we will be using on our course is based on TSMC 0.35um, 3 metal, 2 poly processes as shown below:
 

2.3 SCMOS_SUBM - Sub Micron Rules

The SCMOS layout rules were historically developed for 1.0 to 3.0 micron processes. To take full advantage of advanced submicron processes, the SCMOS rules were revised to create SCMOS_SUBM. By increasing the lambda size for some rules (those that didn't shrink as fast in practice as did the overall scheme of things), the submicron rules allow for use of a smaller value of lambda, and better fit to these small feature size processes. Table 4 lists the differences between SCMOS and SCMOS sub-micron.
 

A user design using the SCMOS rules can be in either Calma GDSII format [2] or Caltech Intermediate Form (CIF version 2.0) [1]. The two are completely interchangable. Note that all submitted CIF and GDS files have already been scaled before submission, and are always in absolute metric units -- never in lambda units.

GDSII is a binary format, while CIF is a plain ASCII text. For detailed syntax and semantic specifications of GDS and CIF, refer to [2] and [1] respectively.

In GDS format, a design layer is specified as a number between 0 and 255 (formerly 63). SCMOS now reserves layer numbers 21 through 62, inclusive, for drawn layout. Layers 0 through 20 plus layers 63 and above can be used by designers for their own purposes.

A partial list of SCMOS layers is shown in Table 5, along with a list by tech-code in Table 6.

Many fine-featured processes utilize CMP (Chemical-Mechanical Polishing) to achieve planarity. Most of the 0.35 micron (and smaller) processes are in this category. Effective CMP requires that the variations in feature density on a layer be restricted.

See the following for more details.

5 Process-Induced Damage (otherwise known as "Antenna Rules") Rules - General Requirements

The "Antenna Rules" deal with process induced gate oxide damage caused when exposed polysilicon and metal structures, connected to a thin oxide transistor, collect charge from the processing environment (e.g., reactive ion etch) and develop potentials sufficiently large to cause Fowler Nordheim current to flow through the thin oxide. Given the known process charge fluence, a figure of exposed conductor area to transistor gate area ratio is determined which guarantees Time Dependent Dielectric Breakdown (TDDB) reliability requirements for the fabricator. Failure to consider antenna rules in a design may lead to either reduced performance in transistors exposed to process induced damage, or may lead to total failure if the antenna rules are seriously violated.