Peter Y. K. Cheung

List of Publications

My publications can be divided into four catagories:

     FPGA, Reconfigurable Computing, Hardware/Software Codesign

      Computed-Aided Design for IC Design

      Digital & Asynchronous Systems, VLSI architecture for Signal Processing, Mixed signal designs

      Others

Linked documents are in Adobe Acrobat (PDF) format.

FPGA, Reconfigurable Computing, Hardware/Software Codesign

  1. Peter Y. K. Cheung, G. A. Constantinides, J. T. de Sousa, "Guest Editors' Introduction: Field Programmable Logic and Applications", IEEE Transactions on Computers, Volume: 53 , Issue: 11 , Nov. 2004, pp.1361 - 1362 (2004).
  2. Nalin Sidahao, George Constantinides, Peter Y. K. Cheung, "Multiple Restricted Multiplication", Field Programmable Logic and Applications, Lecture Notes in Computer Science, Springer-Verlag, 2004. pp.1-10 (2004).
  3. Christos Bouganis, Peter Y. K. Cheung, Jeffrey Ng, Anil A. Bharath, "A Steerable Complex Wavelet Construction and its Implementation on FPGA", Field Programmable Logic and Applications, Lecture Notes in Computer Science, Springer-Verlag, 2004. pp.1-10 (2004).
  4. Pete Sedcole, Peter Y. K. Cheung, George Constantinides, Wayne Luk, "A Structured Methodology for System-on-an-FPGA Design", Field Programmable Logic and Applications, Lecture Notes in Computer Science, Springer-Verlag, 2004. pp.1-10 (2004).
  5. Wim J.C. Melis, Peter Y.K. Cheung, Wayne Luk, "Autonomous Memory Block for Reconfigurable Computing", IEEE International Symposium on Circuits and Systems, ISCAS'04, Vol 2 pp.581-584 (2004).
  6. George A. Constantinides, Peter Y.K. Cheung, Wayne Luk, "Hardware Synthesis from DSP Algorithms", Kluwer Academic Publishers, ISBN 1-4020-7930-3 pp.1-175 (2004).
  7. Calvin T.Y. Sim, C. Toumazou, Peter Y. K. Cheung, "A ratiometric current-mode rational DAC ", Electronics Letters 40 (7) pp.409-410 (2004).
  8. S. Hettiarachi, Peter Y. K. Cheung, "A novel implementation of tile-based address mapping", Design Automation Test Europe (DATE), Vol. 1 pp.306-311 (2004).
  9. Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko, "BIST based Intercconect Fault Location for FPGAs", Field Programmable Logic and Applications, Lecture Notes in Computer Science, Springer-Verlag, 2004. pp.1-10 (2004).
  10. Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides, "Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation", Field Programmable Logic and Applications, Lecture Notes in Computer Science, Springer-Verlag, 2004. pp.1-10 (2004).
  11. Tero Rissa, Peter Y.K. Cheung, Wayne Luk , "SoftSONIC: A Customisable Modular Platform for Video Applications", Field Programmable Logic and Applications, Lecture Notes in Computer Science, Springer-Verlag, 2004. , pp.1-10 (2004)
  12. George A. Constantinides, Peter Y.K. Cheung, Wayne Luk, "Synthesis of Saturation Arithmetic Architectures", ACM Transactions on Design Automation of Electronic Systems 6 (3) (2003).
  13. D.-U. Lee, W. Luk, J. Villasenor, P.Y.K. Cheung, " Hierarchical segmentation schemes for function evaluation", Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), 15-17 Dec. 2003 pp.92 - 99, (2003).
  14. T.K. Lee, A. Derbyshire, W. Luk, P.Y.K. Cheung, " High-level language extensions for run-time reconfigurable systems", Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), 15-17 Dec. 2003, pp.144 - 151 (2003).
  15. George A. Constantinides, P.Y.K. Cheung, Wayne Luk , "Wordlength Optimization for Linear Digital Signal Processing", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22 (10) (2003).
  16. T. Wiangton, C.T. Ewe, Peter Y.K. Cheung, "SONICmole: A debugging environment for the UltraSONIC reconfigurable computer", Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS '03,Volume: 2 , 25-28 May 2003.
  17. N. Sidahao, G. Constantinides, Peter Y.K. Cheung, "Architectures for function evaluation of FPGAs", Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS '03,Volume: 2 , 25-28 May 2003.
  18. T. Wiangtong, Peter Y.K. Cheung , W. Luk, "A Unified Codesign Run-time Environment for the UltraSONIC Reconfigurable Computer", Field Programmable Logic and Applications, Lecture Notes in Computer Science, Springer-Verlag, (2003).
  19. Andrew Royal, Peter Y. K. Cheung , "Globally Asynchronous Locally Synchronous FPGA Architectures", Field Programmable Logic and Applications, Lecture Notes in Computer Science, Springer-Verlag, (2003).
  20. Dong-U Lee, Wayne Luk, John Villasenor, Peter Y.K. Cheung , "Non-uniform Segmentation for Hardware Function Evaluation", Field Programmable Logic and Applications, Lecture Notes in Computer Science, Springer-Verlag, (2003).
  21. Peter Sedcole, Peter Y. K. Cheung , George A. Constantinides, Wayne Luk, "A Reconfigurable Platform for Real-Time Embedded Video Image Processing", Field Programmable Logic and Applications, Lecture Notes in Computer Science, Springer-Verlag, (2003).
  22. T. Wiangtong, Peter Y.K. Cheung , W. Luk , "Cluster-Driven Hardware/Software Partitioning and Scheduling Approach For a Reconfigurable Computer System", Field Programmable Logic and Applications, Lecture Notes in Computer Science, Springer-Verlag, (2003).
  23. S. Hettiaratchi, Peter Y.K. Cheung, "Mesh Partitioning Approach to Energy Efficient Data Layout", Design, Automation and Test in Europe Conference DATE 2003,  pp.1076 - 1081.
  24. T. Wiangtong, Peter Y.K. Cheung, W. Luk, "Multitasking in hardware-software codesign for reconfigurable computer", Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS '03,Volume: 5 , 25-28 May 2003.
  25. Dong-U Lee, W. Luk, J. Villasenor, Peter Y. K. Cheung, "A hardware Gaussian noise generator for channel code evaluation", 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2003 pp.69 - 78.
  26. S. Hettiaratchi, Peter Y.K. Cheung, T.J.W. Clarke, "Energy Efficient Address Assignment Through Minimized Memory Row Switching", The International Conference on Computer Aided Design 2002 (ICCAD), San Jose, 20002.
  27. S. Seng, W. Luk, Peter Y.K. Cheung, "Run-Time Adaptive Flexible Instruction Processors", in M. Glesner, P. Zipf and M. Renovell(eds.) Field Programmable Logic and Applications, Lecture Notes in Computer Science, Vol. 2438, pp. 545-555, Springer-Verlag, 2002.
  28. W.J.C. Melis, Peter Y.K. Cheung, W. Luk, "Image Registration of Real-Time Braodcast Video Using the UltraSONIC Reconfigurable Computer", in M. Glesner, P. Zipf and M. Renovell(eds.) Field Programmable Logic and Applications, Lecture Notes in Computer Science, Vol. 2438, pp. 1148-1151, Springer-Verlag, 2002.
  29. A.A. Gaffar, W. Luk, Peter Y.K. Cheung, N. Shirazi, "Automating Customisation of Floating-Point Designs", in M. Glesner, P. Zipf and M. Renovell(eds.) Field Programmable Logic and Applications, Lecture Notes in Computer Science, Vol. 2438, pp. 523-533, Springer-Verlag, 2002.
  30. T. Wiangtong, Peter Y.K. Cheung, W. Luk, "Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Codesign", International Journal on Design Automation for Embedded Systems, Kluwer Academic Publishers, Volumn 6, pp.425-449, 2002.
  31. Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk, "Image Registration of real-time video data using the SONIC reconfigurable computer platform", IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), California, 2002.
  32. J. Gause, P.Y.K. Cheung, W. Luk, "Reconfigurable Shape-Adaptive Template Matching Architectures", IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), California, 2002.
  33. G. Constantinides, P.Y.K. Cheung, W. Luk, "Optimum Wordlength Allocation", IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), California, 2002.
  34. S. Hettiaratchi, Peter Y.K. Cheung and T.J. Clarke,"Performance-area trade off of hardware address generation for the address decoder decoupled memory", Design, Automation and Test in Europe Conference 4-8 March, 2002, Paris, France.
  35. George A. Constantinides, Peter Y. K. Cheung, and Wayne Luk, "Heuristic Datapath Allocation for Multiple Wordlength Systems", Design, Automation and Test in Europe Conference 13-16 March, 2001, Munich, Germany.
  36. Chakkapas Visavakul, Peter Y. K. Cheung, and Wayne Luk, "A Digit-Serial Structure for Reconfigurable Multipliers", in G. Brebner and R. Woods (eds.) Field Programmable Logic and Applications, Lecture Notes in Computer Science, Vol. 2147, pp. 565-573, Springer-Verlag, 2001.
  37. George A. Constantinides, Peter Y. K. Cheung, and Wayne Luk, "The Multiple Wordlength Paradigm", IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), California, 2001.
  38. George A. Constantinides, Peter Y. K. Cheung, and Wayne Luk, "Multiple Resource Binding", in R.W. Hartenstein, H. Gruenbacher (eds.) Field Programmable Logic and Applications, Lecture Notes in Computer Science, Vol. 1896, pp. 656-655, Springer-Verlag, 2000.
  39. J. Gause, P.Y.K. Cheung, Wayne Luk, "Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT", in R.W. Hartenstein, H. Gruenbacher (eds.) Field Programmable Logic and Applications, Lecture Notes in Computer Science, Vol. 1896, pp. 96-105, Springer-Verlag, 2000.
  40. N. Shirazi, W. Luk, P.Y.K. Cheung, "Framework and Tools for Run-Time Reconfigurable Designs", IEE Proceedings – Computers and Digital Techniques, Vol. 147, No. 3, May 2000, p. 147 - 152.
  41. George A. Constantinides, Peter Y. K. Cheung, and Wayne Luk, "Optimal datapath allocation for multiple-wordlength systems", Electronics Letters, vol. 36, no. 17, 17th August, 2000, p. 1508-1509.
  42. Simon D. Haynes, P.Y.K. Cheung, Wayne Luk, John Stone, "Video Image Processing with the SONIC Architecture", IEEE Computer, April 2000, pp 50 - 57.
  43. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk, "Roundoff-noise shaping in filter design", Proc. IEEE Symposium on Circuits and Systems, ISCAS 2000.
  44. M.V. Scotti, Z. Malik, P.Y.K. Cheung, J. Nelder, "Optimisation of full-custom logic cells using response surface methodology ", IEE Electronics Letters, vol. 36, no. 01, 6th January, 2000, p. 14-16.
  45. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk, "Truncation Noise in Fixed-Point SFGs", IEE Electronics Letters, Vol. 35. No. 23, pp. 2012-2014, November 1999.
  46. S.D. Haynes, P.Y.K. Cheung, W. Luk, J. Stone, "SONIC: A Plug-in Architecture for Video Processing", in Field-Programmable Logic and Applications, P. Lysaght, J. Irvine and R.W. Hartenstein (editors), LNCS 1673, Springer, 1999, pp. 21-30.
  47. G. Constantinides, P.Y.K. Cheung, W. Luk, "Synthia: Synthesis of Interacting Automata targeting LUT-based FPGAs", in P. Lysaght, J. Irvine, R. Hartenstein (eds.) Field Programmable Logic and Applications, Lecture Notes in Computer Science, Vol. 1673, Springer-Verlag, 1999.
  48. S.D. Haynes, P.Y.K. Cheung, W. Luk, J. Stone, "SONIC: A Plug-in Architecture for Video Processing", (poster) IEEE Symposium on FPGAs for Custom Computing Machines, Napa, California, 1999.
  49. Simon D. Haynes, Antonio B. Ferrari, P.Y.K. Cheung, "Flexible Reconfigurable Multiplier Blocks suitable for Enhacning the Architecture of FPGAs", Custom Integrated Circuit Conference, CICC'99.
  50. W. Luk, T.K. Lee, J.R. Rice, P.Y.K. Cheung and N. Shirazi, "Reconfigurable Computing for Augmented Reality", in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), IEEE Computer Society Press, 1999.
  51. S.D. Haynes, A. B. Ferrari, P.Y.K. Cheung, "Algorithms and Structures for Reconfigurable Multiplication Units", the XI Brazilian Symposium on Integrated Circuit Design, October 1998.
  52. N. Shirazi, W. Luk, P.Y.K. Cheung, "Run-Time Management of Dynamically Reconfigurable Hardware", in Field-Programmable Logic and Applications, R.W. Hartenstein and A. Keevallik (editors), LNCS 1482, Springer, 1998, pp. 59-68.
  53. S.D. Haynes, P.Y.K.Cheung, "Configurable multiplier blocks for embedding in FPGAs", Electronics Letters, Vol. 34, No. 7, 638-639, 1998.
  54. S.D. Haynes, P.Y.K. Cheung, "A Reconfigurable Multiplier Array for Video Image Processing Tasks, Suitable for Embedding in an FPGA Structure", IEEE Symposium on FPGAs for Custom Computing Machines, Napa, California, 1998.
  55. N. Shirazi, W. Luk, P.Y.K. Cheung, "Automating Production of Run-Time Reconfigurable Designs", in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), IEEE Computer Society Press, 1998.
  56. N. Zhuang, P.Y.K. Cheung, "Logic synthesis for a fine-grain FPGA", IEE Proceedings – Computers and Digital Techniques, Vol. 145, No. 1, 47 –51, January 1998.
  57. W. Luk, N. Shirazi, P.Y.K. Cheung, "Pipeline morphing and virtual pipelines", in Field-Programmable Logic and Applications, W. Luk, P.Y.K. Cheung and M. Glesner (editors), LNCS 1304, Springer 1997, pp. 111-120.
  58. P.I. Mackinlay, P.Y.K. Cheung, W. Luk, R. Sandiford, "Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research", in Field-Programmable Logic and Applications, W. Luk, P.Y.K. Cheung and M. Glesner (editors), LNCS 1304, Springer 1997, pp. 91-100.
  59. A.S. Chaudhuri, P.Y.K. Cheung, W. Luk, "Reconfigurable data-localised parallel array architecture for morphological algorithms", Proceedings of FPL'97, Sept., 1997.
  60. W. Luk, N. Shirazi, P.Y.K. Cheung, "Compilation Tools for Run-Time Reconfigurable Designs", in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), IEEE Computer Society Press, 1997, pp. 56--65.
  61. O.T. Albaharna, P.Y.K. Cheung, T.J. Clarke, "On the Viability of FPGA-based Integrated Coprocessors", IEEE Symposium on FPGAs for Custom Computing Machines, Napa, California, April 17 - April 19, 1996.
  62. W. Luk, N. Shirazi, P.Y.K. Cheung, "Modelling and Optimising Run-Time Reconfigurable Systems", in Proc. IEEE Symposium on FPGAs for Custom Computing Machines, K.L. Pocek and J. Arnold (editors), IEEE Computer Society Press, 1996, pp. 167-176.
  63. P.Y.K. Cheung, W. Luk, Patrick MacKinlay, "Hardware-Software Cosynthesis for the Riley System", IEE Colloquium on Digest on Hardware-software cosynthesis for reconfigurable systems, February 22, 1996.
  64. O. Albaharna, P.Y.K. Cheung, T.J.W. Clarke, "Area & Time Limitations of FPGA-based Virtual Hardware", International Conference on Computer Design, Cambridge, Mass., Oct., 1994, pp184-189.
  65. O. Albaharna, P.Y.K. Cheung, T.J.W. Clarke, "Virtual Hardware & the Limits of Computational Speed- up", IEEE International Symposium on Circuits and Systems, London, 1994.
Computed-Aided Design of Integrated Circuits 
  1. N. Zhuang, Marcus v. Scotti, P.Y.K. Cheung, "PTM: A Technology Mapper for Pass-Transistor Logic", IEE Proceedings – Computers and Digital Techniques, Vol. 146, No. 1, January 1999, pp13-19.
  2. J.T. Sousa, P.Y.K. Cheung, "Diagnosis of Realistic Interconnect Shorts", Journal of Electronic Testing: Theory and Applications, Vol. 11, 157 – 171, 1997.
  3. G. Barry, P.Y.K. Cheung, C. Toumazou, "Knowledge Engineering for Analogue Design Facilitation", IEEE International Symposiums on Circuits and Systems, June 1997.
  4. J.T. Sousa, P.Y.K. Cheung, "Improved Diagnosis of Realistic Interconnect Shorts", European Design & Test Conference, March 1997.
  5. T. Koskinen, P.Y.K. Cheung, "Hierarchical Tolerance Analysis using Statistical Behavioural Models", IEEE Trans. on CAD of Integrated Circuits and Systems, Vol.15, No.5, May, 1996.
  6. J.T. Sousa, T. Shen, P.Y.K. Cheung, "On Structural Diagnosis for Interconnects", IEEE International Symposiums on Circuits and Systems, Atlanta, May 1996.
  7. N. Zhuang, M.S.T. Benten, P.Y.K. Cheung, "Improved Variable Ordering of BDDs with Novel Genetic Algorithm", IEEE International Symposiums on Circuits and Systems, Atlanta, May 1996.
  8. J.T. Sousa, T. Shen, P.Y.K. Cheung, "Realistic Fault Extraction for Boards", Electronic Design & Test Conference, Feb., 1996.
  9. S. Ahmed, P.Y.K. Cheung, "A Model-Based Approach to Analog Fault Diagnosis Using Techniques from Optimization", The European Design and Test Conference, Paris 1994.
  10. A. Sang-In, P.Y.K. Cheung, "A Method of Representative Fault Selection in Digital Circuits for ATPG", IEEE International Symposium on Circuits and Systems, London, 1994, p.73-76.
  11. S. Ahmed, P.Y.K. Cheung, "Analog Fault Diagnosis -A Practical Approach", IEEE International Symposium on Circuits and Systems, 1994. ISCAS '94., 1994, vol.1, Page(s): 351 -354.
  12. N. Gohar, P.Y.K. Cheung, "A New Schematic-Driven Floorplanning Algorithm for Analog Cell Layout", IEEE International Symposium on Circuits and Systems, Chicago, May 1993, p.1770-1773.
  13. T. Koskinen, P.Y.K. Cheung, "Statistical and Behavioural Modelling of Analogue Integrated Circuits", IEE Proceedings-G, Vol. 140, No.3, June 1993, p171-176.
  14. N. Gohar, P.Y.K. Cheung, "RAVI: A New Fast Multi-Layer Area Routing Algorithm for Analog Cell Layout", Proc. of the 11th European Conference on Circuit Theory and Design, 1993.
  15. S. Ahmed, P.Y.K. Cheung, "A New Approach to Analog Fault Diagnosis Using Circuit Optimisation", Proc. of the 11th European Conference on Circuit Theory and Design, 1993.
  16. N. Gohar, P.Y.K. Cheung, C.K. Pun, "An integrated placement and routing approach to CMOS analog cells", IEEE International Symposium on Circuits and Systems, 1992, p.2981-2984.
  17. T. Koskinen, P.Y.K. Cheung, "Hierarchical Tolerance Analysis using Behavioural Models", IEEE Custom Integrated Circuits Conference, May 1992.
  18. B. Rogel-Favila, A. Wakeling, P.Y.K. Cheung, "AI for Fast Automated Diagnosis of Digital Circuits", 4th Int. Conf. on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, Hawaii, 1991.
  19. N. Gohar, P.Y.K. Cheung, "RACHANA: A Unified Layout Approach for CMOS Analog Cells", European Conf. on Circuit Techniques and Designs, 1991.
  20. T. Koskinen, P.Y.K. Cheung, "Modelling Tolerances and Behaviour in Analogue Cells", Proc. of the IEEE Custom Integrated Circuits Conf., San Diego, 1991, p.8.7.1-8.7.4.
  21. M. Makris, P.Y.K.Cheung, et. el. "CHIPAIDE: a new approach to analogue integrated circuit design", Journal of Semicustom ICs, Vol. 9 No. 2, Elsevier Science Publishers 1991, p13-21.
  22. T. Koskinen, P.Y.K. Cheung, "Behavioural Modelling of A Switched Capacitor Integrator", CEEDA 1991.
  23. B. Rogel-Favila, A. Wakeling, P.Y.K. Cheung, "On Acceleration of Fault Diagnosis Techniques", MILTEST 90.
  24. B. Rogel-Favila, P.Y.K. Cheung, "Deep Reasoning Approach to Sequential Circuit Fault Diagnosis", European Conf. on Circuit Theory and Design, Sept. 1989.
  25. B. Rogel-Favila, P.Y.K. Cheung, "Combinational and Sequential Circuit Fault Diagnosis using AI Techniques", Int. Test Conf., August 1989.
  26. B. Rogel-Favila, P.Y.K. Cheung, "Circuit representation and Diagnosis using Prolog", Proc. 1989 IEEE Int. Symp. on Circuits and Systems, Portland 1989.
Digital & Asynchronous Systems, VLSI architecture for Signal Processing, Mixed signal designs 
  1. D.S. Bormann, P.Y.K. Cheung, "Asynchronous wrapper for heterogeneous systems", IEEE International Conference on Computer Design, October 1997.
  2. P.Y.K. Cheung, M. Scotti, et., "High speed arithmetic design using CPL and DPL logic", Proceedings of the European Solid-State Circuits Conference, Sept 97.
  3. D.S. Bormann, P.Y.K. Cheung, "A novel globally asynchronous locally synchronous sliding window DFT implementation", IFIP International Conference on Very Large Scale Integration,VLSI'97, Gramado, Brazil, August 1997.
  4. R. Wyman, P.Y.K. Cheung, "Bit Plane Differential EZW for the Compression of Video for Variable Bandwidth Channels", IEEE International Symposiums on Circuits and Systems, June 1997.
  5. P.A. Molina, P.Y.K. Cheung, "A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems", Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, The Netherlands, April 1997.
  6. P.A. Molina, P.Y.K. Cheung, D. Bormann, "Quasi-Delay Insensitive Bus for Fully Asynchronous Systems", IEEE International Symposiums on Circuits and Systems, Atlanta, May 1996.
  7. David S. Bormann, Pedro A. Molina, P.Y.K. Cheung, "Combining Asynchronous and Synchronous Circuits using Stretchable Clocks", IEE Colloquium on Digest on Asynchronous System, March, 1996.
  8. Frank K.Y. Mok, A.G. Constantinides, P.Y.K. Cheung, "A VLSI decimation filter for sigma-delta A/D Converters", IEE 2nd International Conference on Advanced A-D and D-A Conversion Techniques and their Applications, Cambridge, 1994, p.36-41.
  9. D. Ostrowski, P.Y.K. Cheung, K. Roubaud, "An outline of the intuitive design of Fuzzy Logic and its Efficient Implementation", Second IEEE International Conference on Fuzzy Systems, March, 1993, p.184-189.
  10. P.Y.K. Cheung, A. Ferrari, P.de Wilde, G. Benyon-Tinker, "Neural Network Processor: A vehicle for teaching system design", IEE Proceedings-G, Vol 139, No. 2, April 1992, p244-248.
  11. V. Fuentes, P.Y.K. Cheung, "A Tag Coprocessor Architecture for Symbolic Languages", IEEE Int. Conf. on Computer Design, Boston 1991, p.370-373.
  12. M.J. Lee, S.W. Wright, C.P. Judge, P.Y.K.Cheung, "High Mobility Ccadmium Selenide Transistors", Int. Display Research Conf., 1991, p.211-214.
  13. P.Y.K. Cheung, E. See "A Comparison of Decimation Filter Architectures for Sigma-Delta A/D Converters", IEEE Int. Symp. on Circuits and Systems, Singapore, 1991, p.1637-1640.
  14. Frank K.Y. Mok, P.Y.K. Cheung, "STRETCH: Self Testing Reliability Evaluation Chip", IEEE Custom Integrated Circuit Conference, 1993, p30.4.1 - 30.4.4.
  15. C.Toumazou, J.Lidgey, P.Y.K. Cheung, "Current-mode Analogue Signal Processing Circuits - a Review of Recent developments", Proc. 1989 IEEE Int. Symp. on Circuit and Systems, Portland 1989.
  16. C.Toumazou, C.Makris, C. Berrah, P.Y.K. Cheung, "A Methodology for Automatic Generation of Analogue Integrated Circuits", European Conf. on Circuit Theory and Design, Sept 1989.
  17. D.A. Chu, F. McCabe, P.Y.K. Cheung, G. Knowles, "SWIFT - a new Symbolic Processor", The 5th Int. Logic Programming Conf., 1988.
  18. R. Kanthan, P.Y.K. Cheung, "A new Technique for Motion Vector Estimation in Interframe Coding of Video Signals", 5th Int. Conf. on Digital Processing Signals in Communication, 1988.
Others 
  1. M. Alwan, P.Y.K. Cheung, "Modelling and Handling Uncertainities in Mobile Robotics", Journal of Intelligent and Fuzzy Systems, Vol. 5, 302-217, 1997.
  2. H. Demirel, T.J.W. Clarke, P.Y.K. Cheung, "Automatic Segmentation of Training Set for Facial Feature Detection", International Conference on Information, Communications and Signal Processing, Singapore, Sept., 1997.
  3. D.J. Ostrowski, P.Y.K. Cheung, "A Fuzzy Logic Appraoch to Handwriting Recognition", in Fuzzy Logic Implementation and Applications, Ed. M.J. Patryra, D.M. Mlynek, Wiley 1996.
  4. H. Demirel, T.J. Clarke, P.Y.K. Cheung, "Apdative Automatic Facial Feature Segmentation", 2nd International Conference on Face and Gesture Recognition, Nov., 1996.
  5. M. Alwan, P.Y.K. Cheung, A. Saleh, N.E.C. Obeid, "Combining Goal-directed, Reactive and Reflexive Navigation in Autonomous Mobile Robots", Proc. IEEE Australia and New Zealand Conf. On Intelligent Information Systems, 1996, pp 346-349.
  6. N.N. Kharma, M.Alwan, P.Y.K. Cheung, "An Incremental Machine Learning Mechanism Applied to Robot Navigation", Proc. IEEE Australia and New Zealand Conf. On Intelligent Information Systems, 1996, pp 325-328.
  7. M. Alwan, O.N.E. Cheikh, N.N. Kharma, P.Y.K. Cheung, "A Three-Layer Hybrid Architecture for Planning in Autonomous Agents", Proc. IEEE Conf. on Intelligent Information Systems, Nov., 1994, p.155-159.
  8. M. Alwan, P.Y.K. Cheung, "Handling Uncertainty Ambiguity and Kinematics in Path Planning", Proc. 3rd International Conference on Automation, Robotics & Computer Vision, Singapore, 1994.

This page maintained by Peter Cheung
Last updated:10 Oct 2004.